The invention relates to a low voltage sense amplifier for an EPROM memory transistor.
In order to read a CMOS EPROM memory transistor forming part of a memory array of rows and columns of transistors, a sense amplifier is coupled to each column.
The drains of the EPROM, transistors, which are connected to the column line, are coupled to the input of the respective sense amplifier. To read a transistor, the column and the input of the sense amplifier are precharged to the main supply voltage VDD.
VDD is typically about 5 volts but in some applications can reach 6 to 8 volts. Precharging the columns to such high voltages can cause some deprogramming of the memory transistors.
This invention seeks to provide a low voltage sense amplifier for an EPROM memory transistor which can operate over a wide range of supply voltage and in which the above mentioned problem is solved.
According to this invention there is provided a low voltage sense amplifier for an EPROM memory transistor comprising a low voltage inverter having an input selectively couplable to the EPROM memory transistor, and an output; means for applying a selectable reference voltage as a supply voltage for the inverter and means responsive to a precharge signal for coupling the selectable reference voltage, as a precharge voltage, to the input of the low voltage inverter.
The means for applying a selectable reference voltage as a supply voltage for the low voltage inverter may comprise a first MOS transistor coupled between a first power supply terminal and a supply line for the inverter, the first MOS transistor having a control electrode for receiving a selectable reference voltage.
The means for coupling the selectable reference voltage as a precharge voltage to the input of the low voltage inverter may comprise a second MOS transistor, coupled between the supply line for the low voltage inverter and the input of the low voltage inverter, and having a control electrode for receiving said precharge signal.
A resistive holding transistor is preferably connected across the second MOS transistor, the holding transistor having a control electrode coupled to be responsive to the output state of the low voltage inverter.
A third MOS transistor may be connected across the said first MOS transistor, the third MOS transistor having a control electrode for receiving a signal indicative of a low supply voltage level of the first power supply, thereby to short circuit the first MOS transistor and couple the first power supply terminal directly to the supply line of the low voltage inverter.
Typically a low-to-high voltage inverter may be provided, coupled to the first power supply terminal and having a low voltage input coupled to the output of the low voltage inverter and having a high voltage output.
In order to speed up switching of the low-to-high voltage inverter in response to the precharge signal, an MOS transistor may be coupled between the low voltage input and a reference terminal, the transistor having a control electrode coupled to receive the precharge signal.
a resistive holding transistor may be coupled between the output of the low-to-high voltage inverter and the first power supply terminal, the transistor having a control electrode coupled to the output of the high voltage inverter via a further inverter.